The present technology relates to a semiconductor device having conductive layers of different heights exposed in a connection hole and a manufacturing method of the same.
LSIs and other semiconductor devices have downsized and grown in sophistication thanks to high-density integration made possible by micro fabrication process. In such a high-density integrated semiconductor device, new ideas have been introduced to reduce the necessary area of the interlayer connection structure for multilayer interconnects. For example, Japanese Patent Laid-Open No. 1997-199586 discloses a semiconductor device having a shared contact structure. In this semiconductor device, the conductive material layers of different heights are connected together with a single connection hole for interlayer connection between multilayer interconnects. As a result, a shared contact structure ensures a smaller necessary area than when a connection hole is provided for each conductive material layer, thus providing high-density integration.
The step of making a connection hole in a shared contact structure is performed as described below. First, a resist pattern having an opening pattern overlapping both of the conductive material layers of different heights is formed by lithography. Next, the interlayer insulating film is etched using the resist pattern as a mask until the shallow conductive material layer is exposed. Next, the surrounding interlayer insulating film is etched using the already-exposed and shallow conductive material layer as a mask until the deep conductive material layer is exposed. The interlayer insulating film is etched as described above using a single resist pattern, thus forming a shared contact structure with different conductive material layers exposed in a connection hole.